The present invention relates to a semiconductor structure with a reduced parasitic capacitance, and more specifically, to a silicon-on-insulator device with a raised source and drain, and a method of making the same.
Parasitic capacitance refers to the undesirable capacitance that exists between parts of a semiconductor device due to the proximity of the parts to each other. All integrated circuit elements (i.e., inductors, diodes, transistors, etc.) have internal capacitance. For example, in a transistor, parasitic capacitance refers to the undesirable capacitance that exists between the source, drain, and gate. Typically, parasitic capacitance can be ignored at low frequencies, but at high frequencies parasitic capacitance can become a problem. For example, at high frequencies, parasitic capacitance between the output and input of a device can act as a feedback path and cause the circuit to oscillate.
A transistor with a raised source/drain is a transistor in which the source and drain are in a layer above the channel region. In a conventional transistor, the channel region is positioned between the source and drain. To reduce parasitic capacitance in a raised source/drain transistor, the distance between each of the raised source and drain to the gate is decreased. However, as the raised source and drain move closer to the gate, the resistance in the source and drain extension regions under the gate spacer increases.